Non-volatile memory devices are used in any application where storage of information has to be maintained even when the memory devices are not powered. In recent years, the market for embedded non-volatile memories (emNVM) has undergone a considerable development. The emNVM are implemented with other devices on a single chip to obtain (electronic) Systems-on-Chip (SoC). The emNVM are implemented in the SoC, for example, to allow post-manufacturing calibration/adjustment (e.g., for analog and/or radio-frequency circuits) by the manufacturer and/or post-manufacturing customization/configuration by the final user. Moreover, the NVM are implemented in SoC where it is desirable to store a limited amount of data in systems such radio frequency identification (RFID) systems.
Several technologic approaches are available to provide an emNVM. Some approaches allow a single programming (or One Time Programmable) of the emNVM, such as poly-fuse or anti-fuse type emNVM.
Other technologic approaches allow performing more write cycles on the emNVM, such as in the case of EEPROM (Electrical Erasable and Programmable Read-Only Memory) or FLASH emNVM, which store a given datum by trapping electric charges in an insulated terminal, or floating gate, of a storage transistor.
However, these types of memory cells use technologies and processes that are not included in standard complementary metal oxide semiconductor (CMOS) technology (to providing the floating gate transistors) usually used to implement SoC. In fact, the storage transistors use an additional polysilicon layer to define their floating gates regions (in addition to that used to define their control gate regions as in the standard CMOS). This difference adds design complexity, which significantly increases the manufacturing cost of the memory devices.
In the art, memory cells of the floating gate type obtainable using standard CMOS processes have been developed. For example, single-poly EEPROMs (or single polysilicon EEPROM) were developed, which may be implemented in standard CMOS technology since they require only one level of polysilicon.
In these memory cells, the floating gate is made from a single polysilicon layer shared between a control capacitor, which dominates and controls the potential of the gate terminal of a MOS transistor connected thereto by capacitive coupling. The program and erase of the cell may occur by hot carrier injection (HCI), such as channel hot electron (CHE), or by Fowler-Nordheim (FN) tunneling in the floating gate in the proximity of the drain region of the transistor floating gate. Italian patent application No. MI2009A002349, of the same Applicant, describes an emNVM that implements single-poly type memory cells.
In addition to the most common injection mechanisms of FN tunneling and CHE, also the injection mechanism called band-to-band tunneling-induced hot electron (BBHE) has been used for the program operation in single-poly EEPROM. U.S. Pat. Nos. 5,940,324 and 5,761,126 describe examples of memory cells programmed by BBHE generated in correspondence of the drain region of a MOS transistor of the memory cell.
Such memory cells use rather complex (and of considerable size on the chip) control circuitry (e.g., row and column decoders, reading and writing unit, etc.) because they must be able to generate and provide to each cell in a matrix of the emNVM a plurality of different voltages, also of high value (compared with a supply voltage of the SoC in which the emNVM is integrated).